The present invention relates to an arithmetic code decoding method and apparatus.
A decoding process of context-based adaptive arithmetic codes specified by the standard “H.264 Main Profile” requires considerable processing performance.
To decode one symbol requires a sequence of at least four steps. In addition, in order to obtain a context index required to decode an arithmetic code for a given symbol, the control must wait for completion of decoding of arithmetic codes for previous symbols, and it is difficult to increase the processing speed by pipelined parallel processes.
Other image-related processes can be speeded up by parallel processes. However, the decoding process of context-based arithmetic codes cannot be speeded up unless the operation frequency is raised.
Conventionally, arithmetic codes are used in JBIG (ITU recommendation T.82) or the like. As a circuit for pipelining and speeding up a circuit for decoding arithmetic codes, various proposals such as patent reference 1, patent reference 2 (to be described later), and the like have been made. These circuits adopt a scheme for simultaneously executing decoding processes of arithmetic codes for symbols using all possible context indices, and adopting a hit context index when a correct context index is determined.
Reference names associated with conventional arithmetic code decoding techniques are:
Patent Reference 1: Japanese Patent Laid-Open No. 2002-33925
Patent Reference 2: Japanese Patent Laid-Open No. 2000-350043
However, in a conventional decoding apparatus that simultaneously and parallelly processes all candidates, the circuit scale increases exponentially with increasing number of pipeline stages.